Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn

• High-speed memory interfaces require the design of optimised low-power and robust analog circuits. This poses significant challenges in sizing due to the inability of using complex modern transistor models, such as the Berkeley Shortchannel IGFET Model (BSIM), to calculate the sizing of the circuits based on hand-analysis. This forces designers to perform iterative simulations, which is time-intensive and error-prone. To address these issues, this work presents an automated sizing approach using pre-computed lookup tables (LUTs) for a 4.3 Gb/s LPDDR4X transceiver in 12nm FinFET technology. The receiver is designed based on gm/ID sizing methodology where look-up tables are used to compute a set of matrices representing the possible design points based on the circuit topology. The design space is constrained by the biasing level, gain, and bandwidth to find an optimised design point in terms of operation region, speed and power. The driver circuit design is automated based on a new algorithm which computes the estimated ON-resistance from the look up table and finds an optimum sizing which fulfills the required impedance range. The calculated sizing of the proposed design approach was used as an input for spectre simulator to compare the simulation results with the input specifications, showing an error margin of less than 1%. Furthermore, the receiver power consumption was evaluated to be 70% less than the work in literature. The proposed driver topology, which uses low voltage swing terminated logic (LVSTL) and near-ground signaling (NGS), provides a 38−120 Ω impedance range at all process, voltage and temperature variations (PVT) for the postlayout results and consumes relatively low power when compared to literature.