Marco Mestice, Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn

• Low Power Double Data Rate 4X (LPDDR4X) is a leading memory standard for mobile applications, delivering data rates up to 4266 Mbps with minimal power consumption. However, its low 0.6V I/O supply voltage and tight timing requirements pose significant challenges to signal integrity and synchronization. This paper presents a full LPDDR4X physical interface (PHY) in GlobalFoundries 12 nm FinFET technology that addresses these issues through novel output driver calibration, digitally controlled delay lines, and de-skewing clock generators. We further incorporate On-Die Termination calibration with comparator offset compensation to ensure robust I/O performance. By integrating a RISC-V subsystem, our PHY enables low-level software control of the memory interface and a fully programmable calibration and training algorithm. The measured results from the fabricated prototype confirm the effectiveness of the proposed strategies, achieving write margins of 300mV/0.61UI at 1.6Gbps and 200mV/0.38UI at 2.133Gbps. Post-layout simulations in all Process-Voltage- Temperature corners at 4.266Gbps show instead write margins of 80mV/0.57UI and 140mV/0.72UI in worst and best corners respectively. The measured output clock amplitude at 2.133GHz is 160mV differential. These findings underscore the feasibility of a LPDDR4X PHY solution that meets stringent performance and power requirements in advanced technology nodes.