Jonas Ney

• In recent years, the throughput and flexibility requirements of communication systems have grown dramatically to support increased data traffic and versatile use cases. In this context, Neural Network (NN)-based algorithms have emerged as a promising approach to satisfy the stringent requirements of future communication systems. In particular, state-of-the-art research has shown remarkable results for various applications such as demapping and equalization, where the adaptability and nonlinearity of NNs can provide advantages as compared to classical solutions. While related work typically focuses on the algorithmic aspects of NN-based communications, it is crucial to also consider the implementation complexity of the proposed methods for practical deployment. Specifically, the hardware design of sophisticated NNs on resource-constrained edge devices like Field-Programmable Gate Arrays (FPGAs) imposes major challenges, ranging from huge design spaces and cross-layer dependencies to high computational complexity combined with limited hardware resources. In contrast to NNs, classical signal processing algorithms have been optimized for decades for efficient implementation. Thus, for fair comparison, it is crucial to evaluate and compare the implementation aspects of NN-based communication systems to classical ones. Therefore, in this work, we bridge the gap between algorithm and implementation by providing efficient FPGA hardware architectures of NNs for communications and edge intelligence. In particular, we analyze and evaluate the implementation aspects of NN-based demapping and equalization. Further, we consider broader application scenarios such as arrhythmia and anomaly detection. In this context, we perform extensive design space explorations, analyze interdependencies between the design layers, provide efficient FPGA architectures, and benchmark our solutions against classical counterparts and conventional hardware platforms. As a result, we demonstrate the adaptability of NN-based demapping on FPGA and develop a hybrid approach combining our solution with a classical one. Moreover, we present a high-performance NN-based equalizer achieving a data rate of more than 40 GBd and show how NN training can be incorporated for high-throughput equalization on FPGA. Additionally, we propose hardware-aware Neural Architecture Search (NAS) for arrhythmia detection, and show how anomaly detection can be performed at the edge. To summarize, we believe that this work provides a crucial step towards the practical deployment of NN-based communication algorithms on resource-constrained devices, while also contributing to the broader field of NN processing at the edge.