A Platform for Analyzing DDR3 and DDR4 DRAMs

  • The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability. Their unique measurement platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority. Furthermore, the authors show how this measurement platform can be used for reverse engineering the internal structure of DRAMs and how this knowledge can be used to improve DRAM’s reliability.

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Author:Matthias Jung, Deepak M. Mathew, Carl C. Rheinländer M.Eng., Christian Weis, Norbert Wehn
Document Type:Conference Proceeding
Language of publication:English
Publication Date:2018/05/30
Year of Publication:2018
Publishing Institute:Technische Universität Kaiserslautern
Date of the Publication (Server):2018/06/04
Tag:DRAM; Measurement; Reverse Engineering
Number of page:8
Faculties / Organisational entities:Kaiserslautern - Fachbereich Elektrotechnik und Informationstechnik
CCS-Classification (computer science):B. Hardware / B.3 MEMORY STRUCTURES / B.3.1 Semiconductor Memories (NEW) (B.7.1) / Dynamic memory (DRAM) (NEW)
DDC-Cassification:6 Technik, Medizin, angewandte Wissenschaften / 621.3 Elektrotechnik, Elektronik